The latest in Quantum Thinking
We demonstrate a modular solid state architecture with deterministic inter-module coupling between four physically separate, interchangeable superconducting qubit integrated circuits.
Learn MoreClassical symmetric encryption algorithms use N bits of a shared secret key to transmit N bits of a message over a one-way channel in an information theoretically secure manner. This paper proposes a hybrid quantum-classical symmetric cryptosystem that uses a quantum computer to generate the secret key.
Learn MoreWe develop a hardware-efficient ansatz for variational optimization, derived from existing ansatze in the literature, that parametrizes subsets of all interactions in the Cost Hamiltonian in each layer. We treat gate orderings as a variational parameter and observe that doing so can provide significant performance boosts in experiments. We carried out experimental runs of a compilation-optimized implementation of fully-connected Sherrington-Kirkpatrick Hamiltonians on a 50-qubit linear-chain subsystem of Rigetti Aspen-M-3 transmon processor.
Learn MoreHere, we demonstrate low-latency feedback with a scalable FPGA decoder integrated into the control system of a superconducting quantum processor. We perform an 8-qubit stability experiment with up to 25 decoding rounds and a mean decoding time per round below 1 \unit\micro, showing that we avoid the backlog problem even on superconducting hardware with the strictest speed requirements.
Learn MoreQuantum approximate optimization is one of the promising candidates for useful quantum computation, particularly in the context of finding approximate solutions to Quadratic Unconstrained Binary Optimization (QUBO) problems. However, the existing QPUs are relatively small, and canonical mappings of QUBO via the Ising model require one qubit per variable, rendering direct large-scale optimization infeasible. In classical optimization, a general strategy for addressing many large-scale problems is via multilevel/multigrid methods, where the large target problem is iteratively coarsened, and the global solution is constructed from multiple small-scale optimization runs. In this work, we experimentally test how existing QPUs perform as a sub-solver within such a multilevel strategy.
Learn MoreWe demonstrate a transformational technique for controllably tuning the electrical properties of fabricated thermally oxidized amorphous aluminum-oxide tunnel junctions. Using conventional test equipment to apply an alternating bias to a heated tunnel barrier, giant increases in the room temperature resistance, greater than 70%, can be achieved.
Learn MoreWe analyze the experimental error budget of parametric resonance gates in a tunable coupler architecture. We identify and characterize various sources of errors, including incoherent, leakage, amplitude, and phase errors. By varying the two-qubit gate time, we explore the dynamics of these errors and their impact on the gate fidelity.
Learn MoreQuantum optimization solvers typically rely on one-variable-to-one-qubit mapping. However, the low qubit count on current quantum computers is a major obstacle in competing against classical methods. Here, we develop a qubit-efficient algorithm that overcomes this limitation by mapping a candidate bit string solution to an entangled wave function of fewer qubits. We propose a variational quantum circuit generalizing the quantum approximate optimization ansatz (QAOA).
Learn MoreSuperconducting quantum processors are one of the leading platforms for realizing scalable fault-tolerant quantum computation (FTQC). The recent demonstration of post-fabrication tuning of Josephson junctions using alternating-bias assisted annealing (ABAA) technique and a reduction in junction loss after ABAA illuminates a promising path towards precision tuning of qubit frequency while maintaining high coherence. Here, we demonstrate precision tuning of the maximum |0⟩→|1⟩ transition frequency of tunable transmon qubits by performing ABAA at room temperature using commercially available test equipment.
Learn MoreIn this study, we performed a comprehensive investigation on the microstructure, superconductivity, and resonator quality factor of Nb films deposited by high-power impulse magnetron sputtering (HiPIMS) and direct current (DC) magnetron sputtering.
Learn MoreHere, we present a resource estimation framework and software tool that estimates the physical resources required to execute specific quantum algorithms, compiled into their graph-state form, and laid out onto a modular superconducting hardware architecture. This tool can predict the size, power consumption, and execution time of these algorithms at as they approach utility-scale according to explicit assumptions about the system's physical layout, thermal load, and modular connectivity. We use this tool to study the total resources on a proposed modular architecture and the impact of tradeoffs between and inter-module connectivity, latency and resource requirements.
Learn MoreWe use a floating tunable coupler to mediate interactions between qubits on separate chips to build a modular architecture. We demonstrate three different designs of multi-chip tunable couplers using vacuum gap capacitors or superconducting indium bump bonds to connect the coupler to a microwave line on a common substrate and then connect to the qubit on the next chip.
Learn MoreWe present a novel transmon qubit fabrication technique that yields systematic improvements in T1 coherence times. We fabricate devices using an encapsulation strategy that involves passivating the surface of niobium and thereby preventing the formation of its lossy surface oxide.
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